Device and method for transposing matrix of video signal and T.V. receiver employing the same

ABSTRACT

Device and method for transposing a matrix of video signals, is disclosed, the device including a memory part, a write control circuit for shifting and writing rows of the matrix of video signals on the memory part by any one unit either of a row unit or column unit, and a read control circuit for shifting and reading the matrix of video signals stored in the memory part by one unit different from the unit in the writing either of the row unit or the column unit,with rows of a matrix of video signal received at the next time written on a portion of the memory part emptied due to the shift in the reading.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a device and a method fortransposing a matrix of video signals, which may be applied to a videodecoder for decoding a matrix of compressed video bitstream such assignals of an MPEG(Moving Picture Expert Group) format.

[0003] 2. Discussion of the Related Art

[0004] As is well known, recently high definition television(HDTV)broadcasting systems have been developed, some of which are put intopilot operation in some of countries. In the pilot operation of the HDTVbroadcasting systems, signals according to the HDTV broadcasting systemsare transmitted, which are capable of being processed in an HDTVreceiver(hereinafter called as HDTV). In the meantime, there are twoclasses of signals in the HDTV system of the ATSC (Advanced TelevisionSystems Committee) of the U.S.A. One class of signal is an HD classsignal for producing images of a high definition, and the other class ofsignal is an SD (Standard Definition) class signal(hereinafter called asSD signal) for producing images of a standard definition. The SD classsignal has a data transmission rate lower than the HD class signal. TheHD TV is adapted to process the two classes of video data, basically.Therefore, there can be four cases of signal transmission betweenbroadcasting stations and HD TV's; the first case is displaying a HDsignal as an HD signal, the second case is displaying an HD signal as anSD signal, the third case is displaying an SD signal as HD class signal,and the fourth is displaying an SD signal as an SD signal. Though thefirst, third and fourth cases have no particular problems in processingthe signals with regard to the system performances, the second casedoes. That is, the second case has problem in that the images appearbroken. Therefore, if an HD signal is to be displayed as an SD classsignal, it is necessary to degrade performance of a received HD signalto some extent. For example, an HD signal of 20 MHz MPEG format shouldbe altered to an SD class signal of 6 MHz MPEG format. This degradationof the HD signal performance implies a drop in the resolution. Ingeneral, the HD signal performance is degraded by removing a portion offrequency band over a certain frequency from the HD signal. An HD signalof an 8×8 matrix having a portion of frequency band over a certainfrequency removed therefrom to suit to the SD class signal is therebyaltered into an 8×4 HD signal. This 8×4 HD signal can be displayed as anSD class signal, with a resolution degraded compared to the 8×8 HDsignal, but without the problem of broken images. In the meantime, an8×8 matrix SD signal can be displayed on an HDTV as it is. Because ofthe aforementioned reason, the HD TV should be adapted to process the8×8 HD signal as well as the 8×4 HD signal. A general HD TV will beexplained with reference to FIGS. 1˜3.

[0005] Referring to FIG. 1, upon receiving a compressed video bit streamfrom a broadcasting station, the general HD TV synchronizes a desiredvideo bitstream in a tuner 10, of the video bitstream received throughan antenna Ant, and demodulates in a demodulator 20. This videobitstream, being an MPEG signal, has a form of matrix. Then, thedemodulated video bit stream is restored in a video decoder 30 andprocessed to a displayable condition in a VDP(Video Display Processor)40. The signal from the VDP 40 is displayed through a displayer 50. Inthis instance, the VDP 40 processes the decoded signals appropriate to aperformance of the displayer 50.

[0006]FIG. 2 illustrates a detail block diagram of the video decoder 30shown in FIG. 1. Upon reception of a matrix of the demodulated video bitstream from the demodulator 20 in FIG. 1, a VLD(Variable Length Decoder)21 therein decodes the demodulated video bit stream to provideDCT(Discrete Cosine Transform) coefficients and motion vectors. The DCTcoefficients are scanned by an inverse scanner 22 and inverse quantizedby the inverse quantizer 23. Then, an IDCT(Inverse Discrete CosineTransformer) 25 makes an inverse discrete cosine transformation of theinverse quantized DCT coefficients to provide spatial pixel values.Here, before the inverse discrete cosine transformation in the IDCT 25,the inverse quantized DCT coefficients are transposed in a transposer 24for easy inverse discrete cosine transformation. On the other hand, amotion compensator 27 uses the motion vectors from the VLD 21 incompensating a reference video frame stored in the frame memory inadvance, and an adder 28 adds a signal from the motion compensator 27and a signal from the IDCT 25, to provide an added value to the VDP 40in FIG. 1.

[0007] Illustrated in FIG. 3 is an example of the transposer 24 formaking alternative read/write of two memories 24 a and 24 b intransposing them.

[0008] Referring to FIG. 3, the transposer 24 is provided with twoSRAM(Static Random Access Memory) 24 a and 24 b each of a 16 bits×64words size and two multiplexed flipflops 24 d and 24 e. Upon receptionof an enable signal in a read/write controller 24 c, the read/writecontroller 24 c provides a read/write controlling signal and a selectingsignal to the first SRAM 24 a and the second SRAM 24 b. The first SRAM24 a and the second SRAM 24 b are operative in opposite manner inresponse to the read/write controlling signal. That is, a first data iswritten on the first SRAM 24 a at the first time, the second SRAM 24 bis left at a disabled state in response to the selecting signal. Then,while the first SRAM 24 a s read, the second a SRAM 24 b is written of asecond data. Thus, the first SRAM 24 a and the second SRAM 24 b are readand written alternatively. The alternative first, second data from thetwo SRAMs 24 a and 24 b are transposed by the multiplexed flipflops 24 dand 24 e. Besides, there are a transposing method disclosed in a U.SPat. No. 4,769,790 by time delaying and a U.S. Pat. No. 5,418,487 usingdual port memories. These two Patents have a disadvantages either in asize of hardware or in a complicated hardware. And, as has beenexplained, the background art transposer 24 shown in FIG. 2 transposesan m×m matrix signal(for example, m=8) using two memories of m×m wordscapacity each. Because of the use of two memories, such a background arttransposer has disadvantages in that the inverse discrete cosinetransformer and the video decoder 30 shown in FIG. 2 have increasedareas and comparatively low operation speed of 100 M sample/sec.

SUMMARY OF THE INVENTION

[0009] Accordingly, the present invention is directed to device andmethod for transposing a matrix of video signals and a televisionreceiver employing the same that substantially obviates one or more ofthe problems due to limitations and disadvantages of the related art.

[0010] An object of the present invention is to provide a method and adevice for transposing a matrix of video signals which can reduce a chiparea of the inverse discrete cosine transformer and, further, an area ofthe video decoder.

[0011] Another object of the present invention is to provide a methodand a device for transposing a matrix of video signals which is operableat fast speed.

[0012] Other object of the present invention is to provide a videodecoder and a television receiver employing the same method and device.

[0013] Additional features and advantages of the invention will be setforth in the description which follows, and in part will be apparentfrom the description, or may be learned by practice of the invention.The objectives and other advantages of the invention will be realizedand attained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

[0014] To achieve these and other advantages and in accordance with thepurpose of the present invention, as embodied and broadly described,there is provided a memory part for writing a matrix of video signalsthereon, a write control circuit shift and writes rows of the videosignals on the memory part by any one unit either of a row unit or acolumn unit. The video signals written on the memory are read from thememory by one unit different from the unit in the writing either of therow unit and the column unit by a read control circuit for transposing.Rows of video signals received at the next time are shifted, and writtenon portions of the memory part emptied in sequence due to the shift inthe reading by one unit opposite to the unit in the reading either ofthe row unit and the column unit in sequence. The memory part mayincludes either one memory on which the matrix of video signals may bewritten or two memory of less capacity, resulting to a reduction of anoccupied area of the memory part. Because rows of video signals receivedat the next time is shifted, and written on portions of the memory partemptied in sequence in the reading, a speed of the transposing becomesfaster.

[0015] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are intended to provide further explanation of theinvention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are included to provide afurther understanding of the invention and are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention:

[0017] In the drawings:

[0018]FIG. 1 illustrates a block diagram showing a system of a generalHD TV, schematically;

[0019]FIG. 2 illustrates a block diagram showing a system of a generalvideo decoder;

[0020]FIG. 3 illustrates a block diagram showing a system of a generaltransposer;

[0021]FIG. 4 illustrates a block diagram showing a system of atransposer in accordance with a first preferred embodiment of thepresent invention;

[0022] FIGS. 5A˜5H illustrate the steps of a process for transposing amatrix of video signals in accordance with the first preferredembodiment of the present invention;

[0023]FIG. 6 explains a transposing of video signals within a matrix inaccordance with the second preferred embodiment of the presentinvention;

[0024] FIGS. 7A˜7H illustrate the steps of a process for transposing amatrix of video signals in accordance with the second preferredembodiment of the present invention;

[0025]FIG. 8A illustrates a block diagram showing a first form of systemof an HD TV having the transposer of the present invention appliedthereto; and,

[0026]FIG. 8B illustrates a block diagram showing a second form ofsystem of an HD TV having the transposer of the present inventionapplied thereto.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0027] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0028] FIRST EMBODIMENT

[0029]FIG. 4 illustrates a block diagram showing a system of atransposer in accordance with a first preferred embodiment of thepresent invention. The transposer includes a memory part 100, a writecontrol circuit 200, a read control circuit 300 and a mode signaldetecting circuit 400. The memory part 100 may include eithermultiplexed flipflops capable of writing m×m video signals thereon or anSRAM using a register file and a cell compiler. The mode signaldetecting circuit 400 determines a received matrix of video bitstream ofbeing 8×8 signals or 8×4 signals and provides a relevant mode signal tothe write control circuit 200 and read control circuit 300. Asexplained, since the HD TV is adapted to suit to an SD signal, the HD TVis required to reduce a performance of received 8×8 HD signals to 8×4 HDsignals to suit to the SD signal. Accordingly, a first embodimenttransposer is designed to be capable of transposing both the 8×8 videosignals and the 8×4 video signals. The operation of the transposer ofthe present invention will be explained, briefly.

[0030] First, the write control circuit 200 shifts, and writes all rowsof the received matrix of signals on the memory part 100 by any one uniteither of a row unit or a column unit to a first direction. The readcontrol circuit shifts, and reads the matrix of signals stored in thememory part 100 by any one unit either of a row unit or a column unitdifferent from the unit in the writing to a second direction. In themeantime, vacant spaces in the memory part 100 caused by the shifting inthe reading are filled with an identical matrix of the next videosignals received successively, with the video signals shifted by thesame unit as the reading to the second direction. In this instance, ifthe writing is made by a row unit and reading is made by acolumm unit,the first direction is a top to bottom direction of the memory part 100and the second direction is a left to right direction of the memory part100. And, if the writing is made by a column unit and reading is made bya row unit, the first direction is the left to right direction of thememory part 100 and the second direction is the top to bottom directionof the memory part 100. When a sequence of lines connecting the writecontrol circuit 200 and the read control circuit 300 to the memory 100is changed to an opposite fashion, the first direction is a right toleft direction and the second direction is a bottom to top direction.

[0031] The matrix of video signals may either be m×m(m=an positiveinteger) or m×m/2(m=a positive even numeral). In general, a received HDsignal and SD signal may be either a matrix of 8×8 signals or a matrixof 8×4 signals. The operation of the transposer shown in FIG. 4 will beexplained for the case when the 8×8 video bitstream or the 8×4 videobitstream is received, separately. First, the case when rows of thereceived 8×8 video signals are written by a row unit on the memory 100will be explained with reference to FIGS. 5A to 5H. In this instance, itis assumed that the memory 100 has a size of 8×8 memory 100. FIG. 5Ashows received 8×8 video signals, and FIG. 5B shows finally transposed8×8 video signals.

[0032] First, referring to FIGS. 5C and 5D, when the 8×8 video signalsare received in the 8×8 memory 100, the write control circuit 200shifts, and writes all the 8 rows of the 8×8 video signals on the 8×8memory by one row unit in sequence from the bottom row to the top row ofthe 8×8 memory 200 at every clock, writing the 8 signals in each of therows of the 8×8 video signals from the right end to the left end of eachrow in the 8×8 memory 100. That is, 8 data are written at every clock,to complete writing of the 8×8 video signals after 8 cycles. Then, asshown in FIGS. 5E and 5F, all the 8×8 video signals written on the 8×8memory 100 are read under the control of the read control circuit 300,with the 8×8 video signals shifted to right side by a column unit, whichis different from the unit in writing, in sequence from right end toleft end. In this instance, the 8 signals in each of the columns onthe8×8 memory 100 are read from the bottom to the top of each column inthe 8×8 memory 100 in sequence. In the meantime, the columns emptied insequence from the left end of the 8×8 memory 100 due to the signal shiftduring the reading are filled with the rows of the 8×8 video signalsreceived at the next time from the top end row to the bottom end row insequence under the control of the write control circuit 300. In thisinstance, the 8 signals in each of the rows are written on each of theemptied columns in the 8×8 memory 100 from the bottom to the top. Then,as shown in FIGS. 5G and 5H, the 8×8 video signals written by a columnunit are read shifted by a row unit in bottom direction, and the rows inthe 8×8 memory 100 emptied started from the top during the reading arefilled with the rows of the next 8×8 video signals, shifted in sequence.Thus, the 8×8 video signals written on the 8×8 memory 100 are transposedwhen they are read out of the memory 100.

[0033] Next, the case when 8 rows of received 8×8 video signals arewritten on the 8×8 memory 100 by a column unit will be explained. Inthis case, since what is required is only a simple change of the unitsin the writing at an initial operation, this operation will be explainedwithout any reference to attached drawings. All the 8 rows in the 8×8signals are written on the 8×8 memory 100 by a column unit, shifting bya column from the right end column to the left end column in the 8×8memory 100 in sequence. In this instance, the 8 signals in each of therows are written from bottom to top of each column of the 8×8 memory100. The 8×8 video signals written on the 8×8 memory 100 are read by arow unit, shifting by one row, from the bottom end row to the top endrow in sequence. In this instance, the 8 signals in each of the rows areread from the right side to the left side. In the meantime, the rowsemptied in sequence from the top end of the 8×8 memory are filled withthe rows of the 8×8 video signals received at the next time shifted fromthe top end row to the bottom end row in sequence, with the 8 signals ineach of the rows written from the right end to the left end of eachemptied row in the 8×8 memory 100.

[0034] Though the above explanation is given for the case when thememory 100 is an m×m memory and the received video signal is also m×m asan example, it is applicable to a case when the received video signal issmaller than m×m(for example, m×m/2). In this case, both the writecontrol circuit 200 and the read control circuit 300 are adapted tocontrol only an m×m/2 region of the m×m memory region. In this instance,the rest of the memory is left void. In this first embodiment, the videosignals are read or written from the right column to the left column andfrom the bottom row to the top row. And, the video signals are writtenor read from the right end to the left end of each row and from thebottom end to the top end of each column. However, this sequence showsan example, and the video signals may be processed in the oppositesequence. That is, the video signals are read or written from the leftcolumn to the right column and from the top row to the bottom row. And,the video signals are written or read from the left end to the right endof each row and from the top end to the botom end of each column.

[0035] Second Embodiment

[0036] A transposing method in accordance with a second embodiment ofthe present invention will be explained. FIG. 6 illustrates a blockdiagram of the second embodiment transposer. The transposer includes twom/2×m/2 memories(for example, 4×4 memories) 500 and 600, a write controlcircuit 700 and a read control circuit 800. Because the secondembodiment transposer is provided to transpose only the m×m/2 videosignals, particularly 8×4 video signals, the mode signal detectingcircuit of the first embodiment is not required.

[0037] First, a case when the rows of the 8×4 signals are written on thememories 500 and 600 by a column unit will be explained with referenceto FIGS. 7A to 7H. FIG. 7A illustrates 8×4 video signals to betransposed, and FIG. 7B illustrates 8×4 video signals transposed. Asshown in FIGS. 7C and 7D, upon reception of the 8×4 video signals, thewrite control circuit 700 classifies the received 8×4 video signals intoa first 4×4 video signals of four odd numbered columns and a second 4×4video signals of four even numbered columns. Then, rows of the first 4×4video signals and the second 4×4 video signals are written on the first4×4 memory 500 and the second 4×4 memory 600 of the two memories 500 and600 by a column unit shifting from a right end column to a left endcolumn in sequence, respectively. In this instance, the four videosignals in each row are written from a bottom end to a top end of eachcolumn of the 4×4 memories 500 and 600. As the 8×4 video signals havefour rows, the write control circuit 700 writes all the 8×4 videosignals on the two 4×4 memories 500 and 600 in 4 cycles, 8 data at everyclock signal. Then, as shown in FIGS. 7E and 7F, the read controlcircuit 800 reads the first 4×4 video signals and the second 4×4 videosignals written on the first 4×4 memory 500 and the second 4×4 memory600 from a top end row to a bottom end row of each of the memories 500and 600, shifting by a row unit in sequence. The video signals are readalternating in the order of the second 4×4 memory 600 and the first 4×4memory 500, with the four video signals in each row in each of thememories 500 and 600 read from the right end to the left end. In themeantime, the rows of the first 4×4 memory 500 and the second 4×4 memory600 emptied in sequence from the top end to the bottom end due to theshift during the reading are filled with the first 4×4 video signals andthe second video signals in the 8×4 video signals received at the nexttime respectively by the write control signal 700, shifting from the topend row to the bottom end row by a row unit in sequence. The 4 signalsin each row are written from the right end to the left end of eachemptied row of each of the memories 500 and 600. Then, as shown in FIGS.7G and 7H, the video signals written by a row unit are read shifting bya column unit for transposing, and the columns emptied during thereading are filled with rows of the next 8×4 video signals shifted by acolumn unit in sequence.

[0038] Next, a case when the received 8×4 video signals are written by arow unit, initially. Since this case represents a case when the unit ofthe writing is changed from a column unit to row unit, this case will beexplained briefly, without reference to any attached drawings.

[0039] First, upon reception of 8×4 video signals, the write controlcircuit 700 classifies the received 8×4 video signal into a first 4×4video signals of odd numbered columns and a second 4×4 video signals ofeven numbered columns. Then, the write control circuit 700 writes eachof the 4 rows of the first 4×4 video signals and the second 4×4 videosignals on the first 4×4 memory 500 and the second 4×4 memory 600respectively by a row unit shifting from the bottom end row to the topend row in sequence. The four signals in each row are written from theright end to the left end of each row of each of the 4×4 memories 500and 600. Then, the read control circuit 800 reads the first 4×4 videosignals and the second 4×4 video signals on the first 4×4 memory 500 andthe second 4×4 memory 600 respectively, shifting from the right endcolumn to the left end column of each of the memories 500 and 600 by acolumn unit in sequence. The second 4×4 memory 600 and the first 4×4memory 500 are read alternatively in the order of the second 4×4 memory600 and the first 4×4 memory 500, with the 4 signals in each column ofeach of the memories 500 and 600 read from the bottom end to the topend. And, the columns in the first 4×4 memory 500 and the second 4×4memory 600 emptied from the left end column to the right end column dueto the shift of the video signals during the reading are filled withrows of the first 4×4 video signals and the second 4×4 video signals ofthe received 8×4 video signals, shifted from the top end row signals tothe bottom row in sequence. In this instance, the 4 signals in each rowof the 4×4 video signals are written from the bottom end to the top endof the emptied columns of each of the memories 500 and 600.

[0040] Though the case when two 4×4 memories are used as the m/2×m/2memories, is taken as an example in the case of reception of m×m/2 videosignals in this second embodiment, other sizes of m/2×m/2(m is an evennumeral) memories may be used for transposing m×m/2 video signals(m is apositive even numeral) of other size matrices. And, identical to thefirst embodiment, each of the 4×4 memories may includes any one ofmultiplexed flipflops, an SRAM or register files. And, as explained inthe first embodiment, the video signals may be processed in a sequenceopposite to the sequence explained above.

[0041]FIG. 8A illustrates a block diagram showing an HDTV employing thetransposer of the present invention. Referring to FIG. 8A, a tuner 1000synchronizes, and receives a matrix of a compressed video bitstream of achannel of many channel signals received from an antenna ANT. The matrixof a compressed video bitstream synchronized by the tuner 1000 isdemodulated by a demodulator 2000 and decoded by a video decoder 4000.Signal from the demodulator 2000 is passed through a pre-parser 3000before decoded in the decoder 4000. As explained, since a general HDTVis adapted to suit to an SD signal, a received HD signal should bereduced of its performance to suit to the SD signal for preventing theproblem of image breakage and the like. The pre-parser 3000 cuts acertain high frequency domain off the received HD signal for reducingperformance of such an HD signal. That is, upon reception of an 8×8 HDsignal from the demodulator 2000, the pre-parser 3000 removes a certainhigh frequency domain from the 8×8 HD signal, to provide 8×4 HD videosignals. In the meantime, if the pre-parser 3000 receives 8×8 SD signalsfrom the demodulator 2000, the preparser 3000 passes the 8×8 SD signalsas they are. A VLD(Variable Length Decoder) 4100 in the video decoder4000 decodes the demodulated video bitstream to provide a matrix ofDCT(Discrete Cosine Transformation) coefficients and motion vectors. Thematrix of DCT coefficients from the VLD 4100 are subjected to inversescanning by an inverse scanner 4200, inverse quantizing by an inversequantizer 4200, and transposing by a transposer 4400. Then, thetransposed matrix of video signals are processed by an IDCT(InverseDiscrete Cosine Transformer) 4500 to produce spatial pixel values. Amotion compensator 4700 compensates a reference frame stored in a framememory 4600 using the motion vectors from the VLD 4100. The adder 4800adds signals from the motion compensator 4700 and the IDCT 4500 andprovided to a VDP(Video Display Processor) 5000. In the meantime, as hasbeen explained, the transposer 4400 includes a memory part for storingthe matrix of video signals from the inverse quantizer 4300, a writecontrol circuit for writing the matrix of video signals from the inversequantizer 4300 on the memory part shifting rows of the matrix of videosignals by one unit either in a row unit or in a column unit insequence, and a read control circuit for reading the matrix of videosignals stored in the memory part shifting by one unit different fromthe unit in the writing in sequence. The write control circuit writesrows of the matrix of video signals from the inverse quantizer 4300 onthe portion of the memory emptied by the shift during the readingshifting by, of the row unit and column unit, one unit identical to theunit in the reading in sequence. The VDP 5000 processes signal from theadder 4800 for display and provides the signal to a display 6000, suchas a cathode ray tube or a liquid crystal display.

[0042] The video bitstream may be an MPEG signal for a HDTVbroadcasting. And, as explained, the matrix of video bitstream may bem×m(m is a positive integer) signals, and the memory part may be amemory which can store the m×m signals. Particularly, the m×m signal maybe 8×8 signals. Or, the received video bitstream may be m×m/2(m is apositive even numeral), and the memory part may includes two memorieseach of which can store m/2×m/2 signals. Particularly, the m×m/2 signalsmay be 8×4 signals, and the m/2×m/2 signals may be 4×4 signals. FIG. 8Billustrates a block diagram showing another system of an HDTV having thetransposer of the present invention applied thereto. As shown in FIG.8B, the system in FIG. 8B is identical to the system of FIG. 8A exceptfor the use of a zonal filter 7000 instead of the preparser 3000. Thatis, the zonal filter 7000 is provided between the VLD 4100 and theinverse scanner 4200 instead of the pre-parser 3000 in FIG. 8A forremoval of an unwanted high frequency domain from signal from the VLD4100. Therefore, the zonal filter 7000 also has a function for alteringthe 8×8 HD signals into the 8×4 HD signals. Moreover, as explained, thememory part also includes any one of at least one multiplexed flipflop,at least one register file, and at least one SRAM.

[0043] As has been explained, because reading of a matrix of videosignals and writing of the next matrix of video signals can be carriedout on the same time, the device and method for transposing a matrix ofvideo signals of the present invention can make IDCT in a video decoderfaster. For example, an IDCT transpose block of 400 M sample/sec can bemade available by the method of the present invention, where an IDCTtranspose block of 100 M sample/sec can be made available by thebackground art method. Further, because what is required is only onememory of a 16 bits×64 bits size for realization of such a four timefaster transpose block, the size of the memory block can be reducedsignificantly.

[0044] Even though the present invention has been explained taking anHDTV as an example in the aforementioned embodiments, the presentinvention can be applicable to a DVD and any devices involving the MPEG.

[0045] It will be apparent to those skilled in the art that variousmodifications and variations can be made in the device and method fortransposing a matrix of video signals and a HDTV receiver employing thesame of the present invention without departing from the spirit or scopeof the invention. Thus, it is intended that the present invention coverthe modifications and variations of this invention provided they comewithin the scope of the appended claims and their equivalents.

What is claimed is:
 1. A method for transposing a matrix of signalsusing a memory, comprising the steps of: (a) shifting, and writing allthe matrix of signals received externally on the memory by any one uniteither of a row unit or a column unit in a first direction; and, (b)shifting, and reading the matrix of signals stored on the memory by onedifferent unit either of a row unit or a column unit in a seconddirection.
 2. A method as claimed in claim 1, further comprising thestep of storing a matrix of signals received in sequence on a portion ofthe memory emptied due to the shift in the reading in the step (b) whileshifting by the one different unit to the second direction.
 3. A methodas claimed in claim 1, wherein, in a case of writing by the row unit andreading by the column unit, the first direction is from a bottom side toa top side of the memory and the second direction is from a left side toa right side of the memory.
 4. A method as claimed in claim 1, wherein,in a case of writing by the column unit and reading by the row unit, thefirst direction is from the left side to the right side of the memoryand the second direction is from the top side to the bottom side of thememory.
 5. A method as claimed in claim 1, wherein the matrix of signalsare m×m(m=a positive integer) signals.
 6. A method as claimed in claim1, wherein the matrix of signals are m×m/2(m=a positive even numeral)signals.
 7. A method for transposing 8×8 video signals using a 8×8memory, comprising the steps of: writing all the 8×8 video signalsreceived in the 8×8 memory thereon by a row unit while shifting 8 rowsof the 8×8 video signals by a row unit from a bottom end row to a topend row of the memory in sequence, with 8 video signals in each rowwritten from a left side to a right side of the each row in the memory;reading the 8×8 video signals written on the memory by a column unitwhile shifting from a right end column to a left end column by a columnunit in sequence, with 8 signals in each column read from a bottom sideto a top side of the each column in the memory; and, storing 8×8 signalsreceived at the next time in the columns in the memory emptied due tothe shift in the reading from the left side in sequence while shiftingrows of the 8×8 video signals from a top end row to a bottom end row insequence, with 8 signals in each row written from the bottom side to thetop side of each of the emptied columns in the memory.
 8. A method fortransposing 8×8 video signals using a 8×8 memory, comprising the stepsof: writing all the 8×8 video signals received in the 8×8 memory thereonby a column unit while shifting 8 rows of the 8×8 video signals by acolumn unit from a right end column to a left end column of the memoryin sequence, with 8 video signals in each row written from a bottom sideto a top side of the each column in the 8×8 memory; reading the 8×8video signals written on the 8×8 memory by a row unit while shiftingfrom a bottom end row to a top end row by a row unit in sequence, with 8signals in each row in the memory read from a right side to a left sideof the each row in the memory; and, storing 8×8 signals received at thenext time in the rows in the memory emptied due to the shift in thereading from the top end in sequence while shifting rows of the 8×8video signals from a top end row to a bottom end row in sequence, with 8signals in each row written from the right end to the left end of eachof the emptied rows in the 8×8 memory.
 9. A method for transposing 8×4video signals using two 4×4 memories, comprising the steps of:classifying received 8×4 video signals into a first 4×4 video signals offour odd numbered columns and a second 4×4 video signals of four evennumbered columns; respectively writing 4 rows of the first 4×4 videosignals and the second 4×4 video signals on a first 4×4 memory and asecond 4×4 memory of the two memories by a row unit while shifting froma bottom end row to a top end row by a row unit in sequence, with 4signals in each row written from a right end to a left end of each rowin each of the memories; respectively reading the first 4×4 videosignals and the second 4×4 video signals on the first 4×4 memory and thesecond 4×4 memory by a column unit while shifting from a right endcolumn to a left end column in each memory by a column unit in sequence,wherein a sequence of the reading is alternative from the second 4×4memory to the first 4×4 memory, with 4 signals in each column in thememories read from the bottom end to the top end; and, respectivelywriting rows of the first 4×4 video signals and the second 4×4 videosignals of the 8×4 video signals received at the next time on thecolumns of the first 4×4 memory and the second 4×4 memory emptied fromthe left end to the right end due to the shift in the reading whileshifting from the top end row to the bottom end row in sequence, withfour signals in each row written from the bottom end to the top end ofeach emptied column in each of the memories.
 10. A method fortransposing 8×4 video signals using two 4×4 memories, comprising thesteps of: classifying received 8×4 video signals into a first 4×4 videosignals of odd numbered columns and a second 4×4 video signals of evennumbered columns; respectively writing 4 rows of the first 4×4 videosignals and the second 4×4 video signals on a first 4×4 memory and asecond 4×4 memory by a acolumm unit while shifting from a right endcolumn to a left end column by a column unit in sequence, with 4 signalsin each row written from a bottom end to a top end of each column ineach of the memories; respectively reading the first 4×4 video signalsand the second 4×4 video signals on the first 4×4 memory and the second4×4 memory by a column unit while shifting from a bottom end row to atop end row in each memory by a row unit in sequence, wherein a sequenceof the reading is alternative from the second 4×4 memory to the first4×4 memory, with 4 signals in each row in the memories read from theright end to the left end; and, respectively writing 4 rows of the first4×4 video signals and the second 4×4 video signals of the 8×4 videosignals received at the next time on the rows of the first 4×4 memoryand the second 4×4 memory emptied from the top end row to the bottom endrow due to the shift in the reading while shifting from the top end rowto the bottom end row in sequence, with four signals in each row of eachof the first and the second video signals written from the right end tothe left end of each emptied row in each of the memories.
 11. A devicefor transposing a matrix of video signals, comprising; a memory part; awrite control circuit for writing rows of all the matrix of videosignals received externally on the memory part by any one unit either ofa row unit or a column unit while shifting by the any one unit; a readcontrol circuit for reading the matrix of video signals stored in thememory part by one unit opposite to the unit in writing either of therow unit or the column unit while shifting by the one unit, wherein thewrite control circuit writes a next matrix of video signals on a portionof the memory part emptied in sequence due to the shift in the readingby the read control circuit while shifting by a unit identical to theunit in the reading in sequence.
 12. A device as claimed in claim 1 1,wherein the matrix of video signals are m×m(m is a positive integer)signals and the memory part includes one memory capable of storing them×m signals.
 13. A device as claimed in claim 1 1, wherein the matrix ofvideo signals are m×m/2(m is a positive even numeral) signals and thememory part includes two memories each capable of storing the m/2×m/2signals.
 14. A device as claimed in claim 11, wherein the memory partincludes at least one memory of multiplexed flipflops.
 15. A device asclaimed in claim 11, wherein the memory part includes at least onememory of an SRAM.
 16. A device as claimed in claim 11, wherein thememory part includes at least one memory of register files.
 17. A devicefor transposing a matrix of video signals, comprising: a 8×8 memory; amode signal detecting circuit for determining signals receivedexternally of being 8×8 video signals or 8×4 video signals and providinga mode signal relevant to the determination; a write control circuit forwriting either of the 8×8 video signals or 8×4 video signals on the 8×8memory entirely while making an appropriate shifting of rows of signalsbeing written by any one unit either of a row unit or a column unit inresponse to the mode signal; a read control circuit for reading thesignals stored in the 8×8 memory by any one unit opposite to the unit inthe writing either of the row unit or the column unit while making anappropriate shifting of rows of the signals by the any one unit oppositeto the unit in the writing in response to the mode signal, wherein thewrite control circuit writes video signals received at the next time ona portion of the 8×8 memory emptied due to the shift in the reading bythe read control circuit while making an appropriate shifting by theunit identical to the unit in reading in response to the mode signal.18. A device as claimed in claim 17, wherein the 8×8 memory includes atleast one memory of 8×8 multiplexed flipflops.
 19. A device as claimedin claim 17, wherein the 8×8 memory includes at least one memory of an8×8 SRAM.
 20. A device as claimed in claim 17, wherein the memoryincludes at least one memory of 8×8 register files.
 21. A device fortransposing a matrix of video signals, comprising: a first 4×4 memory; asecond 4×4 memory; a write control circuit for respective writing of allof four odd numbered columns and four even numbered columns of 8×4 videosignals received externally on the first 4×4 memory and the second 4×4memory by one unit either of a row unit or a column unit while shiftingby the one unit; and, a read control circuit for reading the 8×4 videosignals written on the first 4×4 memory and the second 4×4 memory by oneunit opposite to the one unit in the writing either of the row unit orthe column unit, with a sequence of the reading alternating from thesecond 4×4 memory to the first 4×4 memory, wherein the write controlcircuit writes four rows of 8×4 video signals received at the next timeon portions of the two memories emptied due to the shift in the readingby the read control Beast circuit by one unit identical to the one unitin the reading either of the row unit or the column unit while shiftingthe four rows of the 8×4 video signals by one unit identical to the oneunit in the reading either of the row unit or the column unit.
 22. Adevice as claimed in claim 21, wherein each of the 4×4 two memoriesincludes multiplexed flipflops.
 23. A device as claimed in claim 21,wherein each of the 4×4 two memories includes an SRAM.
 24. A device asclaimed in claim 21, wherein each of the 4×4 two memories includesregister files.
 25. A video decoder, comprising: a variable lengthdecoder(VLD) for decoding a received video bit stream in a form of amatrix to provide a matrix of discrete cosine transformation(DCT)coefficients and motion vectors; an inverse scanner for inverse scanningthe matrix of DCT coefficients provided from the VLD; an inversequantizer for inverse quantizing a signal from the inverse scanner; atransposer for transposing a matrix of signals from the inversequantizer, the transposer including, a memory part, a mode signaldetector for determining a matrix form of a signal from the inversequantizer and providing a relevant mode signal, a write control circuitfor writing the signals from the inverse quantizer on the memory part byany one unit either of a row unit or a column unit while shifting rowsof the signals by the any one unit in sequence appropriately in responseto the mode signal, a read control circuit for reading a matrix ofsignals written on the memory part by one unit different from the oneunit in the writing either of the row unit or the column unit whileshifting the matrix of signals by the one unit different from the oneunit in the writing either of the row unit or the column unit insequence, wherein the write control circuit writes the next signals fromthe inverse quantizer on a portion of the memory part emptied due to theshift in the reading by one unit identical to the one unit in thereading while shifting rows of the next signals by the one unitidentical to the one unit in the reading in sequence; an inversediscrete cosine transformer(IDCT) for subjecting the transposed signalsto inverse cosine transformation to provide spatial pixel values; aframe memory for storing a reference frame; a motion compensator forcompensating the reference frame using the motion vedor from the VLD;and, an adder for adding the signal from the motion compensator and thesignal from the IDCT.
 26. A video decoder as claimed in claim 25,wherein the video bitstream in a form of a matrix is an MPEG signal. 27.A video decoder as claimed in claim 25, wherein the matrix includes m×msignals(m is a positive integer) and the memory part is a memory onwhich the m×m signals can be written.
 28. A video decoder as claimed inclaim 27, wherein the m×m signals are 8×8 video signals.
 29. A videodecoder as claimed in claim 25, wherein the matrix includes m×m/2signals(m is a positive even numeral) and the memory part includes twomemories on each of which m/2×m/2 signals can be written.
 30. A videodecoder as claimed in claim 29, wherein the m×m/2 signals are 8×4 videosignals and the m/2×m/2 signals are 4×4 video signals.
 31. A videodecoder as claimed in claim 25, further comprising a pre-parser in frontof the VLD for removing an unwanted high frequency domain from the videobitstream.
 32. A video decoder as claimed in claim 25, furthercomprising a zonal filter between the VLD and the inverse scanner forremoving an unwanted high frequency domain by removing some ofcoefficients from signals of the VLD signals.
 33. A video decoder asclaimed in claim 29, wherein the memory part includes at least onemultiplexed flipflops.
 34. A video decoder as claimed in claim 25,wherein the memory part includes at least one SRAM.
 35. A video decoderas claimed in claim 29, wherein the memory part includes at least oneregister file.
 36. A television receiver, comprising: a tuner forreceiving a matrix of compressed video bitstream; a demodulator fordemodulating the received matrix of video bitstream; a video decoder fordecoding the matrix of video bitstream from the demodulator, the videodecoder including, a VLD for decoding the demodulated video bitstream toprovide a matrix of DCT coefficients and motion vectors, an inversescanner for subjecting the matrix of DCT coefficients from the VLD toinverse scanning, an inverse quantizer for subjecting the inversescanned matrix of DCT coefficients to inverse quantizing, a transposerfor transposing the inverse quantized matrix of signals, an IDCT forsubjecting the transposed matrix of signals to inverse cosinetransformation to converting the transposed matrix of signals into, andproviding spatial pixel values, a frame memory for storing a referenceframe, a motion compensator for compensating the reference frame storedin the frame memory using the motion vectors from the VLD, and an adderfor adding the signals from the motion compensator and the signals fromthe IDCT; the transposer including, a memory part for storing the matrixof signals, a write control circuit for writing rows of the IDCT signalson the memory part by any one unit either of a row unit or a column unitwhile shifting the rows of the IDCT signals by the any one unit insequence, and a read control circuit for shifting and writing thesignals stored in the memory pat by any one unit opposite to the oneunit in the writing either of the row unit and the column unit insequence, wherein rows of a next matrix of signals from the inversequantizer are shifted and written on portions of the memory emptied dueto the shift in the reading by one unit identical to the unit in thereading either of the row unit or the column unit; a video displayprocessor(VDP) for storing the signals from the video decoder,processing the signals displayable, and providing the signal insequence; and, a display part for displaying the signals from the VDP ona screen.
 37. A television receiver as claimed in claim 36, wherein thevideo bitstream is an MPEG signal.
 38. A television receiver as claimedin claim 36, wherein the received video bistream is m×m(m is a positiveinteger) signals and the memory part includes a memory in which the m×msignals can be stored.
 39. A television receiver as claimed in claim 38,wherein the m×m signals are 8×8 video signals.
 40. A television receiveras claimed in claim 36, wherein the received video bitstream is m×m/2(mis a positive even numeral) signals and the memory part includes twomemories in each of which m/2×m/2 signals can be stored.
 41. Atelevision receiver as claimed in claim 39, wherein the m×m/2 signalsare 8×4 video signals and the m/2×m/2 signals are 4×4 video signals. 42.A television receiver as claimed in claim 39, further comprising apreparser in front of the VLD for removing an unwanted high frequencydomain from the demodulated video bitstream.
 43. A television receiveras claimed in claim 41, wherein the preparser changes 8×8 HD signalsinto 8×4 HD signals.
 44. A television receiver as claimed in claim 36,further comprising a zonal filter between the VLD and the inversequantizer for removing an unwanted high frequency domain from thesignals from the VLD.
 45. A television receiver as claimed in claim 43,wherein the zonal filter changes 8×8 HD signals into 8×4 HD signals. 46.A television receiver as claimed in claim 36, wherein the memory partincludes at least a multiplexed flipflop.
 47. A television receiver asclaimed in claim 36, wherein the memory part includes at least aregister file.
 48. A television receiver as claimed in claim 36, whereinthe memory part includes at least an SRAM.